CPU Emulator Docs

Quick Start

Open CPU EMULATOR from the GAMES menu.
Write assembly in ASSEMBLY SOURCE.
Click ASSEMBLE + LOAD (program loads at 0x0500).
Use STEP for single-instruction execution or RUN for continuous execution.
Use STOP to halt the run loop and RESET to reset CPU/memory state.
Use TERMINAL I/O to queue keyboard input for memory-mapped reads and inspect character output.

Architecture Overview

16-bit CPU, 16 general-purpose registers: R0-RF.
64 KB byte-addressable memory: 0x0000-0xFFFF.
Program counter defaults to 0x0500 after reset.
Instruction encoding is variable length (1 to 4 bytes): opcode + optional RR byte + optional 16-bit immediate.

Flags and Execution State

CF: comparison/conditional flag used by conditional branches and returns.
PF: privileged-memory access flag (1=full memory access).
IF: interrupt-in-progress flag.
BIF: block interrupts when set.
OV: signed arithmetic overflow flag.
CA: carry/borrow flag.
ZF: zero-result flag.
LMB/LME: local memory begin/end region used when PF=0.

Memory Map (conventions used by emulator)

Range	Purpose
`0x0001`	JSR software-stack pointer byte (stack base is `0x0200`).
`0x00F0`	Terminal input status register (`1` when input bytes are queued).
`0x00F1`	Terminal input data register (read pops one queued byte).
`0x00F2`	Terminal output register (write byte/ASCII char to append terminal output).
`0x00F3`	Terminal output clear register (write any value to clear output).
`0x0100-0x01FF`	Interrupt vector table; each vector entry is a 16-bit handler address.
`0x0200-0x02FF`	Internal JSR return-address stack storage.
`0x0400-0x042A`	Saved execution context during interrupt handling.
`0x0500...`	Default program load/execution region.

Assembly Syntax

Registers: R0 to RF.
Immediates: decimal (42) or hex (0x002A).
Comments: start with ; or #.
Labels: LOOP: on their own line or before an instruction.
Label immediates are supported (e.g. LFI R1, LOOP).
Accepted operand forms:
- OP
- OP Rn
- OP Rn, Rm
- OP Rn, imm
- OP imm

Sample Program

START:
  LFI R1, 0x0005
  LFI R2, 0x0003
  ADD R1, R2
  HALT

Complete Instruction Reference

Opcode	Mnemonic	Operands	Behavior
0x00	NOOP	-	No operation.
0x01	LFI	Rn, imm	Load 16-bit immediate into `Rn`.
0x02	LFA	Rn, Rm	Load 16-bit word from address in `Rm` into `Rn`.
0x03	LFAL	Rn, Rm	Load byte at address in `Rm` into low byte of `Rn`.
0x04	LFAH	Rn, Rm	Load byte at address in `Rm` into high byte of `Rn`.
0x05	STO	Rn, Rm	Store 16-bit word from `Rn` to address in `Rm`.
0x06	STOL	Rn, Rm	Store low byte of `Rn` to address in `Rm`.
0x07	STOH	Rn, Rm	Store high byte of `Rn` to address in `Rm`.
0x08	MVR	Rn, Rm	Move `Rm` into `Rn`.
0x09	SWR	Rn, Rm	Swap full 16-bit values of `Rn` and `Rm`.
0x0A	SWP	Rn	Swap high/low bytes within `Rn`.
0x0B	NOT	Rn	Bitwise NOT on `Rn`; updates `ZF`.
0x0C	AND	Rn, Rm	`Rn = Rn & Rm`; updates `ZF`.
0x0D	OR	Rn, Rm	`Rn = Rn \| Rm`; updates `ZF`.
0x0E	XOR	Rn, Rm	`Rn = Rn ^ Rm`; updates `ZF`.
0x0F	NOR	Rn, Rm	`Rn = ~(Rn \| Rm)`; updates `ZF`.
0x10	SHR	Rn, Rm	Logical right shift `Rn` by `Rm & 0xF`; updates `ZF`.
0x11	SHL	Rn, Rm	Left shift `Rn` by `Rm & 0xF`; updates `ZF` and `CA`.
0x12	ROR	Rn, Rm	Rotate `Rn` right by `Rm & 0xF`.
0x13	ROL	Rn, Rm	Rotate `Rn` left by `Rm & 0xF`.
0x14	ADD	Rn, Rm	`Rn = Rn + Rm`; updates `CA`, `OV`, `ZF`.
0x15	SUB	Rn, Rm	`Rn = Rn - Rm`; updates `CA`, `OV`, `ZF`.
0x16	MUL	Rn, Rm	Multiply; low 16 bits in `Rn`, sets `CA/OV` if wide result overflows.
0x17	DEV	Rn, Rm	Divide: quotient to `Rn`, remainder to `Rm`; divide-by-zero triggers interrupt 0x00.
0x18	EVE	Rn, Rm	Set `CF` if equal.
0x19	EVGT	Rn, Rm	Set `CF` if `Rn > Rm`.
0x1A	EVLT	Rn, Rm	Set `CF` if `Rn < Rm`.
0x1B	EVGTE	Rn, Rm	Set `CF` if `Rn >= Rm`.
0x1C	EVLTE	Rn, Rm	Set `CF` if `Rn <= Rm`.
0x1D	EVNOT	-	Invert `CF`.
0x1E	EVST	-	Set `CF = 1`.
0x1F	EVSF	-	Set `CF = 0`.
0x20	EVOF	-	Copy `OV` into `CF`.
0x21	EVZF	-	Copy `ZF` into `CF`.
0x22	EVCA	-	Copy `CA` into `CF`.
0x23	JMP	Rn	Absolute jump to address in `Rn`.
0x24	JMPC	Rn	Jump to `Rn` if `CF=1`.
0x25	JRA	Rn	Relative jump ahead by `Rn` from current instruction address.
0x26	JRS	Rn	Relative jump back by `Rn` from current instruction address.
0x27	JRAC	Rn	Conditional relative jump ahead by `Rn` if `CF=1`.
0x28	JRSC	Rn	Conditional relative jump back by `Rn` if `CF=1`.
0x29	JRIA	imm	Relative jump ahead by immediate.
0x2A	JRIS	imm	Relative jump back by immediate.
0x2B	JRIAC	imm	Conditional relative jump ahead by immediate if `CF=1`.
0x2C	JRISC	imm	Conditional relative jump back by immediate if `CF=1`.
0x2D	JTSR	Rn	Call subroutine at `Rn`; pushes return address.
0x2E	JTSRC	Rn	Conditional call if `CF=1`.
0x2F	RFSR	-	Return from subroutine (pop return address).
0x30	RFSRC	-	Conditional return if `CF=1`.
0x31	HALT	-	Stop execution.
0x32	INT	Rn	Trigger interrupt with low byte of `Rn` as ID.
0x33	INTI	imm	Trigger interrupt with immediate low byte as ID.
0x34	RFI	-	Return from interrupt by restoring saved context.
0x35	SBI	-	Set interrupt block (`BIF=1`).
0x36	CBI	-	Clear interrupt block (`BIF=0`).
0x37	SPF	-	Enable privileged memory access (`PF=1`).
0x38	CPF	-	Disable privileged memory access (`PF=0`).
0x39	SLMB	Rn	Set local memory begin from `Rn`.
0x3A	SLME	Rn	Set local memory end from `Rn`.

CPU Emulator + Assembler Documentation

Quick Start

Architecture Overview

Flags and Execution State

Memory Map (conventions used by emulator)

Assembly Syntax

Sample Program

Complete Instruction Reference